The present invention relates to semiconductor memories, and more particularly to improvements in semiconductor memories of the type integrated on-chip in large scale and very large scale semiconductor monolithic integrated circuits, such improvements being directed to, and affording, reduced power consumption.
A semiconductor memory of the "on-chip" type is a memory disposed and arranged within the chip (i.e., the semiconductor body) of a monolithic integrated circuit in integral association with other portions of the body constituting, for example, the master clock, logic, control, and other functional portions of the total circuit. Such an on-chip memory is to be distinguished from a semiconductor memory of the stand-alone type, where in effect the semiconductor body containing the memory constitutes only the memory, and does not include other significant portions not directly associated and involved with the functioning of the memory.
Other significant differences between on-chip semiconductor memories and those of the stand-alone type derive from the fact that a stand-alone memory is an asynchronous device and an on-chip memory is not. This means that the internal control clock signals of the stand-alone memory are generated from asynchronous external signals. By contrast, with an on-chip memory the clock signals for the memory are internally derived and provided on the chip from, and in synchronization with, the output of the same clock used to time the logic, control and other functional portions of the total circuit.
It is also characteristic of on-chip memories that accesses are generally much more frequent than is usually the case in a stand-alone memory. For example, with an instruction read only memory (ROM) on-chip in association with a micro-code driven compute engine, memory access would normally occur in every clock cycle, in contrast to the merely intermittent clock cycle access normally characteristic of a stand-alone memory.
Briefly the present invention is derived in part from the recognition that in semiconductor memories of the ROM or RAM (random access memory) type, having bit lines and intersecting word lines and an array of memory cells associated with the intersections of such bit lines and word lines, much of the power consumption results from the requirement for pre-conditioning to a selected voltage state (so-called "pre-charging") and subsequent discharging of the bit lines.
Such pre-charging of the bit lines normally involves causing the bit line voltage to assume a selected, usually high, level, so as to avoid disturbing both selected and unselected memory cells during a read-out or other desired memory cell exercising operation. This pre-charging normally occurs during every access cycle, and hence this power consumption problem is particularly significant and burdensome in on-chip semiconductor memories where access is normally most frequent and usually occurs during every clock cycle.
The larger the memory in terms of number and length of bit lines, the greater is the corresponding pre-charging power consumption because of the large parasitic bit line capacitances. Such capacitance-related power consumption, of course, also increases with the operational frequency or clock rate of the memory.
Prior art attempts to solve problems of excessive power consumption in stand-alone memories have been directed to measures for pre-charging only selected ones, rather than all, of the bit lines, and to other measures for monitoring the state of charge of the bit lines, recharging them only when and as the charge voltage falls below a desired level. However, such measures involve complex additional monitoring and control circuitry and do not provide practical or satisfactory solutions to the power consumption problem of on-chip memories where the logic, control and other functional portions integrated in the monolithic chip circuit of which the memory is a part make addition of further circuitry undesirable if not totally impractical.